Voltage peaks or voltage pulses, for example voltage pulses caused by electrostatic discharge (ESD) or electrical overstress (EOS), can lead to damage or to degradation of reliability in discrete semiconductors or in integrated circuits (ICs) comprising a plurality of semiconductor elements in a common semiconductor body such as a semiconductor die. Voltage peaks may be caused by electrical charge, for example charge which may result from an ESD event. In the case of an ESD event, circuit elements around a pin where a discharge current is introduced may be forced into extreme operating conditions, for example electric breakdown. This may lead to undesired damage of circuit elements, for example melting of semiconductor or metal regions and/or gate oxide degradation or breakdown. Protection elements such as ESD structures may be connected between circuit pins for protecting circuit blocks against damage caused by ESD events. Insulated gate field effect transistors (IGFETs) such as lateral double diffused metal oxide semiconductor field effect transistors (lateral DMOSFETs or LDMOSFETs) at circuit pins, for example transistors having a low on-state resistance for switching load currents may also be capable of absorbing discharge currents without damage, for example due to their size, design and/or upstream driver circuits. When applying self-protecting LDMOSFETs to an integrated circuit, chip area saving may be achieved by omitting ESD structures at related circuit pins.
It is desirable to improve self-protection of LDMOSFETs.